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The HTL8237 is a synchronous implementation of the industry standard 8237A Direct Memory Access Controller. The DMA controller is fully pin and software compatible with the 8237A and support four independently programmable channels. Each channel is capable of performing memory-to-memory, memory-to/from- peripheral and memory initialisation tasks. The DMA controller is written in vendor neutral VHDL and can be used for ASIC/FPGA implementations. The HTL8237 supports four DMA channels each with an address range of 64K bytes/words. An address can be auto incremented, decremented or put on hold to support initialisation tasks. A channel can be programmed to automatically re- initialise after each transfer. The DMA controller support 4 modes of operations, single, block, demand and cascade. Single mode allows one transfer before returning the bus to the processor, this mode ensures that the processor can always access the bus between DMA transfers. Block mode transfers a programmed number of words without returning the bus. During the transfer the bus request signal is kept asserted until all words have been transferred or the End-Of-Process(EOP) signal is asserted. In demand mode the peripheral continues to transfer data until exhausted or when the preprogrammed number of transfers has been reached or when EOP signal is asserted. The final mode is the cascade mode which is used to extend the number of channels by cascading additional 8237 controller(s).

Key Features

Functional and pin compatible with the industry 82C37A 4 Independent Maskable DMA Channels 4 modes of operations     Single Transfer Mode     Block Transfer Mode     Demand Transfer Mode     Cascade Mode Memory to Memory Transfer (8bits) Initialise Memory (8bits) No internal tri-state busses Fully synthesizable Written in technology independent VHDL Asynchronous reset Lowest cost commercial 82C37 core
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8237 DMA Controller

HTL8237