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The HTL8254 is a synchronous implementation of the industry standard 8254/82C54 Programmable Interval Timer (PIT) adaptor. The PIT can be used for a wide range of timing and counting functions. The PIT provides three independently programmable 16-bits down-counters. Each counter can be used for a number of timing task such as event counter, elapse time counter, one-shot counter, baudrate generator, complex waveform generator, square wave generator and many more. The HTL8254 support 6 programmable counter modes, mode0: Interrupt on Terminal Count, mode1: Hardware Retriggerable One-Shot, mode2: Rate Generator, mode3: Square Wave mode, mode4: Software Triggered Mode and mode5: Hardware Retriggerable Strobe.

Key Features

Functional compatible with the industry standard PIT 8254 6 Programmable counter modes Status Read-Back command Wide range of timing functions:     Real-Time Clock     Event Counter     Digital one-shot     Prog. rate generator     Square Wave generator     Binary rate multiplier     Complex waveform generation     Complex motor control Simple Processor/uController Interface Binary and BCD counting options No internal tri-state busses Fully synthesizable Written in technology independent VHDL Lowest cost commercial 8254 IP core
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PIT-8254 Timer


Area and Performance

The table below shows a push button implementation of the standalone core for the 3 major FPGA vendors. The values given are an indication of the required area and performance. No pin number, slewrate or I/O type was specified. Mentor Graphic's Precision RTL 2007a.8 was used for synthesis.


The HTL8254 is delivered in synthesizable VHDL source code. The source code is fully documented and can be synthesized using any modern synthesis tool. A partial self-checking VHDL testbench is included which verifies the 6 operating modes. For evaluation the HTL8254 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL8254 is instantiated together with the HTL80186 processor, an HTL8259 Interrupt controller, an Opencores 16750 UART,  a 146818 compatible Real Time Clock, an HTL8255 Parallel Port Interface and 40Kbyte of embedded SRAM. No VHDL source files will be supplied in this case.
Vendor FPGA Type Area Fmax P&R
Actel ProASIC3 A3P060-2 VQFTP100 1339 Tiles (359 Seq) 101.3MHz Designer 8.4
Altera CycloneIII EP3C5E 144C-7 742 LE (328 FF) 144.8MHz Quartus 8
Xilinx Spartan3E 3S100 CP132-4 483 Slices 100.5MHz ISE 11.1