Home Commercial IP FreeIP SCBuilder Contact
© 2001-2018 HT-Lab
The HTL8255 is a synchronous implementation of the industry standard 8255/82C55 Programmable Parallel Interface(PPI) adaptor. The PPI can be used for a wide range of parallel I/O interface tasks. The PPI provides three 8 bits parallel I/O ports (Port A, B and C) that can be configured in 3 different modes. In mode0 each one of the three 8 bits ports can be programmed as either an input or as an output port. One of the ports (PortC) can be split into a 4 bits input and a 4 bits output port. In mode1 the ports can be programmed as a strobed I/O port with part of PortC used for handshake and interrupt control signals. The final mode2 is used for strobed bi-directional I/O with some of PortC signals used for handshake and interrupt signals.

Key Features

Functional compatible with the industry standard PPI 8255 24 bidirectional I/O lines 3 modes of operations         Mode 0 - Basic I/O         Mode 1 - Strobed I/O         Mode 2 - Bi-Directional Strobed I/O Individual bit set and reset operations on PortC 8-bits Status Register 8-bits Control Register with readback Interrupt Control operations No internal tri-state busses Fully synthesisable Written in technology independent VHDL Asynchronous reset Lowest cost commercial 8255 core
All trademarks mentioned on this web page are trademarks of their respective owners.
PPI-8255 Parallel I/O Controller 


Area and Performance

The table below shows a push button implementation of the standalone core for the 3 major FPGA vendors. The values given are an indication of the required area and performance. No pin number, slewrate or I/O type was specified. Mentor Graphic's Precision RTL 2007a.8 was used for synthesis.


The HTL8255 is delivered in synthesizable VHDL source code. The source code is fully documented and can be synthesized using any modern synthesis tool. A self-checking VHDL testbench is included which verifies the 3 operating modes. For evaluation the HTL8255 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL8255 is instantiated together with the 80186 processor, a 16550 UART and 40Kbyte of SSRAM. No VHDL source files will be supplied in this case. Note: The original 82C55A semiconductor device does not have a clock input and as such the HTL8255 + Craignell40 board can not be used as a replacement without adding a clock.
Vendor FPGA Type Area Fmax P&R
Actel ProASIC3 A3P030-2 VQFTP100 317 Tiles (78 Seq) 180MHz Designer 8.0
  Iglo AGL030V2 VQ100 317 Tiles (78 Seq) 76.7MHz  
Altera CycloneII EP2C5 F256C 156 LE (76 FF) 291MHz Quartus 7.2
  StratixIII EP3SE50 F484C 125 LE (81 FF) 480MHz  
Xilinx Spartan2 2s15 VQ100 118 Slices 130MHz ISE 9.2i
  Virtex5 5VLX30 FF324 117 Slices 492MHz