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The HTL8259 is a synchronous implementation of the industry standard 8259/8259A
Programmable Interrupt Controller (PIC). The PIC can be used to extend the number of
interrupt lines on a microcontroller/processor. Although the PIC is normally used in an
x86 design, the VHDL source code can easily be modified to adopt to a non-x86 style
The HTL8259 provide a wide range of vectored interrupt handling and ternination
modes. The controller can be programmed for fixed, priority and polled mode of
operation. Interrupt inputs can either be level or edge triggered. A single HTL8259
controller can handle up to 8 vectored priority interrupts. Without any glue logic multiple
HTL8259 can be cascaded to provide up to 64 vectored priority interrupts. This number can further be increased by using the
The HTL8259 is delivered in vendor neutral VHDL and can be synthezised for a wide range of FPGA/ASIC's.
Functional compatible with the industry standard PIC 8259
End Of Interrupt modes
Automatic with Rotation
Specific with Rotation
Fully and Special Fully nested mode
Special Mask mode
Cascade mode with Master/Slave selection
Edge and Level triggered interrupt inputs
No internal tri-state busses
Written in technology independent VHDL
Lowest cost commercial 8259 core
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PIC-8259A Interrupt Controller
Area and Performance
Differences with the original 8259
The table below shows a push button implementation of the standalone core for the 2 major FPGA vendors. The values given are
an indication of the required area and performance. No pin number, slewrate, I/O type etc was specified. Xilinx ISE and Altera
Quartus were used for synthesis and Place&Route.
||CycloneII EP2C5 F256C
There are a number of differences between the original 28 pins VLSI device from Intel and others and the HTL8259,
Due to the synchronous nature the HTL8259 requires a clock and reset signal.
Two additional signals are available to control top level tri-state buffers for the databus and cascade signals.
The HTL8259 has not been validated for the 8080 and 8085 processors although the logic for the 3 byte call sequence and
register settings are available.
The HTL8259 is delivered in synthesizable vendor neutral VHDL source code. The source code is fully documented and can be
synthesized using any modern synthesis tool. A self-checking VHDL testbench is included which partly verifies the different
For evaluation the HTL8259 can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTL8259 is
instantiated in dual cascade mode together with an HTL80186 processor, the HTL16550 UART, a Real Time Clock, the HTL8254
Timer unit and 40Kbyte of SSRAM. No VHDL source files will be supplied in this case, just a bitstream.