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The HTLSPIm is a Master Serial Peripheral Interface (SPI) controller. The controller can be used to interface to a wide range of SPI slave devices such as ADC, DAC, CAN, Ethernet, SD cards, Display controllers etc.  To minimise the CPU overhead the HTLSPIm is enhanced with user configurable FIFOs, Interrupt and DMA support. To support as many SPI slave devices as possible the HTLSPIm can be programmed for a wide variety of configurations. The Slave Select (SS) signals can be individually be programmed for active high or active low. The first SCLK edge after SS has been asserted can be delayed for up to 3 SCLK periods. For streaming purposes, the SS signal can make a transition between each word which is required for some devices which latch or output data on the rising edge of SS. A programmable 8 bits divider can be used to generate an SCLK clock from clk/2 up to clk/256. The HTLSPIm can be programmed to start filling the FIFO as soon as a transition is detected on the MISO pin. This is useful for Secure Digital memory cards which start a response byte with a 0. The HTLSPIm core is written in generic synthesisable VHDL and can be used for FPGA or ASIC implementation.

Key Features

3-wire synchronous Interface Full Duplex User configurable FIFOs Interrupt Support with 7 different sources DMA support Programmable CLK to SCLK divider (CLK/2..CLK/512) Programmable SCLK Polarity (CPOL) Programmable SCLK Phase (CPHA) 8 SS outputs with programmable polarity Programmable SS to first SCLK edge delay Programmable SS transition between words Secure Digital card support MISO stuck at one detection Programmable SPI word length (8..16 bits) Programmable Least or Most significant bit first Programmable FIFO interrupt trigger level Simple 8bits uProcessor/uController Interface Fully synchronous design Async or Sync reset control Positive edge clocking Written in technology independent VHDL Lowest cost commercial SPI Master IP core
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SPI Master Controller 


Area and Performance


The table below shows a push button implementation of the standalone core for the 3 major FPGA vendors. The values given are a rough indication of the required area against performance. The default settings are use for Synthesis and Place&Route. Other than a clock constraint of 100MHz no other constraints were specified. Higher performance and/or lower utilisation can be achieved by using different synthesis techniques and/or tweaking various settings. Configuration: 64Byte TX/RX FIFO, DMA, SS Polarity Control
Vendor FPGA Type Area Fmax P&R
Actel ProASIC3 A3P060-2 VQFTP100 512 comb, 165 seq, 2 Mem blocks 102.73 MHz Libero 9.0
Altera CycloneIII EP3C5E 144C-7 421 LE, 1024 memory bits 102.7 MHz Quartus 9.1
Xilinx Spartan3E 3S500 CP132-4 205 Slices, 2 BRAMs 102.5 MHz ISE 11.4
The HTLSPIm is delivered in synthesizable vendor neutral VHDL source. The source code is fully documented and can be synthesized using any modern synthesis tool. A self-checking VHDL testbench is included which verifies the different modes. For evaluation the HTLSPIm can be supplied on a low-cost FPGA development board from Enterpoint Ltd. The HTLSPIm is instantiated together with the HTL80186 processor, an HTL8259 Interrupt controller, an HTL8254 Programmable Timer,  a 146818 compatible Real Time Clock, an HTL8255 Parallel Port Interface, a Watchdog timer and 40Kbyte of embedded SRAM. No VHDL source files will be supplied in this case.
Configuration: No FIFO, no SS Polarity control
Vendor FPGA Type Area Fmax P&R
Actel ProASIC3 A3P060-2 VQFTP100 375 comb, 127 seq 106.9 MHz Libero 9.0
Altera CycloneIII EP3C5E 144C-7 276 LE 118.04 MHz Quartus 9.1
Xilinx Spartan3E 3S500 CP132-4 163 Slices 103.17 MHz ISE 11.4